In the field of wireless telecommunication, polar transmitter architectures are known which may be used to decompose an input signal from the baseband into a magnitude signal and a phase signal, which are subjected to an envelope modulation and a phase modulation, respectively, and then combined and amplified by a power amplifier. Polar transmitters use processors for performing a rectangular-to-polar conversion of the input signal which may be an I/O signal. By means of the rectangular-to-polar conversion, the input signal is represented in its polar coordinates. The polar transmitter may use a cordic (coordination rotation digital computer) processor receiving the I/O input signal and outputting the polar signal. Digital transmitters including a cordic processor may operate at high frequencies and with high accuracy. This results in a high power consumption which will significantly increase with an increase of the clock frequency at which the cordic algorithm operates, for example, when the required clock frequency is increased in future wireless networks.
Computing devices may require the processing of data which may represent a signal in Cartesian coordinates. On the basis of such a signal it may be desired to calculate a trigonometric function. Such an operation may take place in a processor, a graphical processor and/or a mathematical coprocessor of the computing device, like a desktop computer, a laptop, a smart phone. In such environments, the cordic algorithm may be implemented, for example directly in hardware, for performing operations like addition, subtraction or bit shifting. For determining the polar coordinates on the basis of a rectangular input signal, the cordic algorithm calculates iteratively both the magnitude and the angle of the resulting vector using a “magnitude path” and an “angle” path. A significant amount of hardware elements is required for implementing the operations mentioned above which, in turn, results in a higher power consumption of the device and/or may increase latencies in case signals are processed along the respective paths at different speeds so that before entering a new iteration, a latency is introduced until all signals in the different paths have been processed for the current iteration.